(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to improve the integrity of a capacitor device.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices featuring sub-micron features, has allowed device fabrication costs to be reduced while also allowing the performance of these same devices to be increased. Advances in specific semiconductor fabrication disciplines such as photolithographic and dry etching has enabled smaller device features to be routinely obtained, thus allowing decreases in unwanted performance degrading capacitances to be realized. In addition integrated fabrication of specific elements such as capacitor structures, along with other semiconductor logic components have allowed process costs to be reduced. To minimize the number of cost consuming photolithographic procedures needed for the integration of a capacitor cell in a logic type process sequence, care must be used to adequately fabricate key capacitor features. If specific photolithographic masking steps directed at exposing areas wherein capacitor regions will be formed via ion implantation procedures are marginalized, inadequate formation of the capacitor region will occur resulting in a capacitor depletion phenomena deleteriously influencing capacitor cell performance.
The present invention will describe a process in which the formation of a capacitor cell is integrated into a logic device fabrication process flow, wherein only one photolithographic masking step is used to define a capacitor cell, thus requiring no additional photolithographic steps. The disclosed fabrication sequence insures the integrity of the capacitor cell, reducing a capacitor depletion phenomena which can occur with other integrated process sequences not using this present invention. Prior art such as attorney docket No. TS01-1579/1580/284, filed Mar. 27, 2003, Ser. No. 10,400,401, as well as published U.S. patent application No. 20020094697, filed Nov. 2, 2001, Ser. No. 10/033,690, describe methods of forming capacitor cells, and of integrating the fabrication of the capacitor cell with the formation of logic devices. However these prior art do not employ the novel process steps and sequence featured in the present invention.